SH7052 datasheet(442/919 Pages) RENESAS

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12.2.2

Timer Control/Status Register (TCSR)

The timer control/status register (TCSR) is an 8-bit readable/writable register. (TCSR differs from

other registers in that it is more difficult to write to. See section 12.2.4, Register Access, for

details.) TCSR performs selection of the timer counter (TCNT) input clock and mode.

Bits 7 to 5 are initialized to 000 by a power-on reset, and in hardware standby mode and software

standby mode. Bits 2 to 0 are initialized to 000 by a power-on reset and in hardware standby

mode, but retain their values in software standby mode.

Bit:

OVF

WT/

TME

—

CKS2

CKS1

CKS0

Initial value:

R/W:

R/(W)*

R/W

Note: * The only operation permitted on the OVF bit is a write of 0 after reading 1.

• Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00 in

interval timer mode. This flag is not set in the watchdog timer mode.

Bit 7: OVF

Description

No overflow of TCNT in interval timer mode

(Initial value)

[Clearing condition]

When 0 is written to OVF after reading OVF

TCNT overflow in interval timer mode

• Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or

interval timer. When TCNT overflows, the WDT either generates an interval timer interrupt

(ITI) or generates a

WDTOVF signal, depending on the mode selected.

Bit 6: WT/

Description

Interval timer mode: interval timer interrupt (ITI) request to the CPU

when TCNT overflows

(Initial value)

Watchdog timer mode:

WDTOVF signal output externally when TCNT

overflows. (Section 12.2.3, Reset Control/Status Register (RSTCSR),

describes in detail what happens when TCNT overflows in watchdog

timer mode.)

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