SH7052 datasheet(444/919 Pages) RENESAS

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12.2.3

Reset Control/Status Register (RSTCSR)

RSTCSR is an 8-bit readable/writable register. (RSTCSR differs from other registers in that it is

more difficult to write. See section 12.2.4, Register Access, for details.) It controls output of the

internal reset signal generated by timer counter (TCNT) overflow. RSTCR is initialized to H'1F by

input of a reset signal from the

RES pin, but is not initialized by the internal reset signal generated

by overflow of the WDT. It is initialized to H'1F in hardware standby mode and software standby

mode.

Bit:

WOVF

RSTE

RSTS

—

Initial value:

R/W:

R/(W)*

R/W

Note:

Only 0 can be written to bit 7 to clear the flag.

• Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that TCNT has overflowed (H'FF

to H'00) in watchdog timer mode. This flag is not set in interval timer mode.

Bit 7: WOVF

Description

No TCNT overflow in watchdog timer mode

(Initial value)

[Clearing condition]

When 0 is written to WOVF after reading WOVF

Set by TCNT overflow in watchdog timer mode

• Bit 6—Reset Enable (RSTE): Selects whether to reset the chip internally if TCNT overflows in

watchdog timer mode.

Bit 6: RSTE

Description

Not reset when TCNT overflows

(Initial value)

LSI not reset internally, but TCNT and TCSR reset within WDT.

Reset when TCNT overflows

• Bit 5—Reset Select (RSTS): Selects the kind of internal reset to be generated when TCNT

overflows in watchdog timer mode.

Bit 5: RSTS

Description

Power-on reset

(Initial value)

Manual reset

• Bits 4 to 0—Reserved: These bits always read 1. The write value should always be 1.

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