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SH7052 Datasheet(PDF) 473 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 473 Page - Renesas Technology Corp |
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473 / 919 page ![]() 447 • Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in synchronous mode because no stop bits are added. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Bit 3: STOP Description 0 One stop bit (Initial value) In transmitting, a single bit of 1 is added at the end of each transmitted character. 1 Two stop bits In transmitting, two 1-bits are added at the end of each transmitted character. • Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, settings of the parity enable (PE) and parity mode (O/ E) bits are ignored. The MP bit setting is used only in asynchronous mode; it is ignored in synchronous mode. For the multiprocessor communication function, see section 14.3.3, Multiprocessor Communication. Bit 2: MP Description 0 Multiprocessor function disabled (Initial value) 1 Multiprocessor format selected • Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the internal clock source of the on-chip baud rate generator. Four clock sources are available: P φ, Pφ/4, Pφ/16, or Pφ/64 (P φ is the peripheral clock). For further information on the clock source, bit rate register settings, and baud rate, see section 14.2.8, Bit Rate Register. Bit 1: CKS1 Bit 0: CKS0 Description 00P φ (Initial value) 1P φ/4 10P φ/16 1P φ/64 |
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