SH7052 datasheet(519/919 Pages) RENESAS

519 / 919 page

493

In receiving, the SCI operates as follows:

1. The SCI synchronizes with serial clock input or output and initializes internally.

2. Receive data is shifted into RSR in order from the LSB to the MSB. After receiving the data,

the SCI checks that RDRF is 0 so that receive data can be loaded from RSR into RDR. If this

check passes, the SCI sets RDRF to 1 and stores the receive data in RDR. If the check does not

pass (receive error), the SCI operates as indicated in table 14.11 and no further transmission or

reception is possible. If the error flag is set to 1, the RDRF bit is not set to 1 during reception,

even if the RDRF bit is 0 cleared. When restarting reception, be sure to clear the error flag.

3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in SCR,

the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the receive-

data-full interrupt enable bit (RIE) in SCR is also set to 1, the SCI requests a receive-error

interrupt (ERI).

Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 14.24

shows a sample flowchart for transmitting and receiving serial data simultaneously. The procedure

is as follows (the steps correspond to the numbers in the flowchart):

1. SCI initialization: Set the TxD and RxD pins using the PFC.

2. SCI status check and transmit data write: Read the serial status register (SSR), check that the

TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to

0. The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1.

3. Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the

error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving

cannot resume if ORER remains set to 1.

4. SCI status check and receive data read: Read the serial status register (SSR), check that RDRF

is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.

The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.

5. Continue transmitting and receiving serial data: Read the RDRF bit and RDR, and clear RDRF

to 0 before the MSB (bit 7) of the current frame is received. Also read the TDRE bit to check

whether it is safe to write (if it reads 1); if so, write data in TDR, then clear TDRE to 0 before

the MSB (bit 7) of the current frame is transmitted. When the DMAC is started by a transmit-

data-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared

automatically. When the DMAC is started by a receive-data-full interrupt (RXI) to read RDR,

the RDRF bit is cleared automatically.

Note:

In switching from transmitting or receiving to simultaneous transmitting and receiving,

clear both TE and RE to 0, then set both TE and RE to 1 simultaneously.

SH7052 Datasheet(PDF) 519 Page - Renesas Technology Corp