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SH7052 Datasheet(PDF) 587 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 587 Page - Renesas Technology Corp |
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587 / 919 page  561 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the A/D converter. A/D0 10-bit D/A ADDR0 to ADDR1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 + – Comparator Sample-and- hold circuit A/D conversion control circuit AVcc AVss AVref Module data bus Module data bus ADI0 interrupt signal ADI1 interrupt signal ATU0 ADTRG0 ADCR0, ADCR1: ADCSR0, ADCSR1: A/D control registers 0 and 1 A/D control/status registers 0 and 1 A/D1 ADDR12 to ADDR15 AN12 AN13 AN14 AN15 ATU0 ADDR0 to ADDR15: ADTRGR0: A/D data registers 0 to 15 A/D trigger register0 10-bit D/A + – Comparator Sample-and- hold circuit A/D conversion control circuit Internal data bus Internal data bus Figure 16.1 A/D Converter Block Diagram |
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