SH7052 datasheet(590/919 Pages) RENESAS

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16.1.4

Table 16.2 summarizes the A/D converter’s registers.

Table 16.2

A/D Converter Registers

Name

Abbreviation

R/W

Initial

Value

Address

Access

Size*

A/D data register 0 (H/L)

ADDR0 (H/L)

H'0000

H'FFFFF800

8, 16

A/D data register 1 (H/L)

ADDR1 (H/L)

H'0000

H'FFFFF802

8, 16

A/D data register 2 (H/L)

ADDR2 (H/L)

H'0000

H'FFFFF804

8, 16

A/D data register 3 (H/L)

ADDR3 (H/L)

H'0000

H'FFFFF806

8, 16

A/D data register 4 (H/L)

ADDR4 (H/L)

H'0000

H'FFFFF808

8, 16

A/D data register 5 (H/L)

ADDR5 (H/L)

H'0000

H'FFFFF80A

8, 16

A/D data register 6 (H/L)

ADDR6 (H/L)

H'0000

H'FFFFF80C

8, 16

A/D data register 7 (H/L)

ADDR7 (H/L)

H'0000

H'FFFFF80E

8, 16

A/D data register 8 (H/L)

ADDR8 (H/L)

H'0000

H'FFFFF810

8, 16

A/D data register 9 (H/L)

ADDR9 (H/L)

H'0000

H'FFFFF812

8, 16

A/D data register 10 (H/L)

ADDR10 (H/L)

H'0000

H'FFFFF814

8, 16

A/D data register 11 (H/L)

ADDR11 (H/L)

H'0000

H'FFFFF816

8, 16

A/D data register 12 (H/L)

ADDR12 (H/L)

H'0000

H'FFFFF820

8, 16

A/D data register 13 (H/L)

ADDR13 (H/L)

H'0000

H'FFFFF822

8, 16

A/D data register 14 (H/L)

ADDR14 (H/L)

H'0000

H'FFFFF824

8, 16

A/D data register 15 (H/L)

ADDR15 (H/L)

H'0000

H'FFFFF826

8, 16

A/D control/status register 0

ADCSR0

R/(W)*

H'00

H'FFFFF818

8, 16

A/D control register 0

ADCR0

R/W

H'0F

H'FFFFF819

8, 16

A/D trigger register 0

ADTRGR0

R/W

H'FF

H'FFFFF76E

A/D control/status register 1

ADCSR1

R/(W)*

H'00

H'FFFFF838

8, 16

A/D control register 1

ADCR1

R/W

H'0F

H'FFFFF839

8, 16

A/D trigger register 1

ADTRGR1

R/W

H'FF

H'FFFFF72E

Notes: Register accesses consist of 6 or 7 cycles for byte access and 12 or 13 cycles for word

access.

1. A 16-bit access must be made on a word boundary.

2. Only 0 can be written to bit 7, to clear the flag.

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