SH7052 datasheet(612/919 Pages) RENESAS

612 / 919 page

586

16.4.5

A/D Converter Activation by ATU-II

The A/D0 and A/D1 converter modules can be activated by an A/D conversion request from the

ATU-II’s channel 0 interval timer.

To activate the A/D converter by means of the ATU-II, set the TRGE bit to 1 in the A/D control

ATU-II channel 0 interval timer A/D conversion request is generated after these settings have been

made, the ADST bit set to 1. The timing from setting of the ADST bit until the start of A/D

conversion is the same as when 1 is written into the ADST bit by software.

16.5

Interrupt Sources and DMA Transfer Requests

The A/D converter can generate an A/D conversion end interrupt request (ADI0 or ADI1) upon

completion of A/D conversions. The ADI interrupt can be enabled by setting the ADIE bit in the

A/D control/status register (ADCSR) to 1, or disabled by clearing the ADIE bit to 0.

The DMAC can be activated by an ADI interrupt. In this case an interrupt request is not sent to the

CPU.

When the DMAC is activated by an ADI interrupt, the ADF bit in ADCSR is automatically

cleared when data is transferred by the DMAC.

See section 9.4.2, Example of DMA Transfer between A/D Converter and On-Chip Memory, for

an example of this operation.

16.6

Usage Notes

The following points should be noted when using the A/D converter.

1. Analog input voltage range

The voltage applied to analog input pins during A/D conversion should be in the range AV

SS ≤

n ≤ AVref.

2. Relation between AV

SS, AVCC and VSS, VCC

When using the A/D converter, set AV

CC = 5.0 V ±0.5 V, and AVSS = VSS. When the A/D

converter is not used, set AV

SS = VSS , and do not leave the AVCC pin open.

3. AV

ref input range

Set AV

ref = 4.5 V to AVCC when the A/D converter is used, and AVref ≤ AVCC when not used.

If conditions above are not met, the reliability of the device may be adversely affected.

SH7052 Datasheet(PDF) 612 Page - Renesas Technology Corp