SH7052 datasheet(609/919 Pages) RENESAS

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16.4.3

Analog Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit in A/D0, A/D1, and A/D2. The A/D

converter samples the analog input at time t

D (A/D conversion start delay time) after the ADST bit

is set to 1, then starts conversion. Figure 16.6 shows the A/D conversion timing.

The A/D conversion time (t

CONV) includes tD and the analog input sampling time (tSPL). The length

of t

D is not fixed, since it includes the time required for synchronization of the A/D conversion

operation. The total conversion time therefore varies within the ranges shown in table 16.4.

In scan mode, the t

CONV values given in table 16.4 apply to the first conversion. In the second and

subsequent conversions, t

CONV is fixed at 512 states when CKS = 0 or 256 states when CKS = 1.

Table 16.4

A/D Conversion Time (Single Mode)

CKS = 0

CKS = 1

Item

Symbol

Min

Typ

Max

Min

Typ

Max

Unit

A/D conversion start

delay time

—

States

(

φ base)

Input sampling time

SPL

—

128

——

—

A/D conversion time

CONV

518

—

532

262

—

268

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