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SH7052 Datasheet(PDF) 618 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 618 Page - Renesas Technology Corp |
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618 / 919 page  592 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the AUD. PC output circuit Address buffer Data buffer Mode control Internal bus Bus controller Peripheral module bus On-chip memory On-chip peripheral module CPU AUDATA0 AUDATA1 AUDATA2 AUDATA3 AUDRST AUDMD AUDCK AUDSYNC Figure 17.1 AUD Block Diagram 17.2 Pin Configuration Table 17.1 shows the AUD’s input/output pins. Table 17.1 AUD Pins Function Name Abbreviation Branch Trace Mode RAM Monitor Mode AUD data AUDATA3 to AUDATA0 Branch destination address output Monitor address/data input/output AUD reset AUDRST AUD reset input AUD reset input AUD mode AUDMD Mode select input (L) Mode select input (H) AUD clock AUDCK Serial clock ( φ/2) output Serial clock input AUD sync signal AUDSYNC Data start position identification signal output Data start position identification signal input |
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