SH7052 datasheet(620/919 Pages) RENESAS

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594

Pin Functions in Branch Trace Mode

Description

AUDCK

This pin outputs 1/2 the operating frequency (

φ/2).

This is the clock for AUDATA synchronization.

AUDSYNC

This pin indicates whether output from AUDATA is valid.

High: Valid data is not being output

Low: An address is being output

AUDATA3 to

AUDATA0

1. When

AUDSYNC is low

When a program branch or interrupt branch occurs, the AUD asserts

AUDSYNC and outputs the branch destination address. The output order is

A3 to A0, A7 to A4, A11 to A8, A15 to A12, A19 to A16, A23 to A20, A27 to

A24, A31 to A28.

2. When

AUDSYNC is high

When waiting for branch destination address output, these pins constantly

output 0011.

When an branch occurs, AUDATA3 to AUDATA2 output 10, and AUDATA1 to

AUDATA0 indicate whether a 4-, 8-, 16-, or 32-bit address is to be output by

comparing the previous fully output address with the address output this time

(see table below).

AUDATA1, AUDATA0

Address bits A31 to A4 match; 4 address bits A3 to A0 are to

be output (i.e. output is performed once).

Address bits A31 to A8 match; 8 address bits A3 to A0 and A7

to A4 are to be output (i.e. output is performed twice).

Address bits A31 to A16 match; 16 address bits A3 to A0, A7

to A4, A11 to A8, and A15 to A12 are to be output (i.e. output

is performed four times).

None of the above cases applies; 31 address bits A3 to A0, A7

to A4, A11 to A8, and A15 to A12, A19 to A16, A23 to A20,

A27 to A24, and A31 to A28 are to be output (i.e. output is

performed eight times).

SH7052 Datasheet(PDF) 620 Page - Renesas Technology Corp