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SH7052 Datasheet(PDF) 638 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 638 Page - Renesas Technology Corp |
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638 / 919 page ![]() 612 18.3.3 Port B IO Register (PBIOR) Bit: 15 14 13 12 11 10 9 8 PB15 IOR PB14 IOR PB13 IOR PB12 IOR PB11 IOR PB10 IOR PB9 IOR PB8 IOR Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 PB7 IOR PB6 IOR PB5 IOR PB4 IOR PB3 IOR PB2 IOR PB1 IOR PB0 IOR Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W The port B IO register (PBIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port B. Bits PB15IOR to PB0IOR correspond to pins PB15/PULS5/SCK2 to PB0/TO6A. PBIOR is enabled when port B pins function as general input/output pins (PB15 to PB0) or serial clock pins (SCK0, SCK1, SCK2), and disabled otherwise. When port B pins function as PB15 to PB0 or SCK0, SCK1, and SCK2, a pin becomes an output when the corresponding bit in PBIOR is set to 1, and an input when the bit is cleared to 0. PBIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. 18.3.4 Port B Control Registers H and L (PBCRH, PBCRL) Port B control registers H and L (PBCRH, PBCRL) are 16-bit readable/writable registers that select the functions of the 16 multiplex pins in port B. PBCRH selects the functions of the pins for the upper 8 bits of port B, and PBCRL selects the functions of the pins for the lower 8 bits. PBCRH and PBCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in software standby mode or sleep mode. |
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