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SH7052 Datasheet(PDF) 676 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 676 Page - Renesas Technology Corp |
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676 / 919 page ![]() 650 18.3.18 Port J IO Register (PJIOR) Bit: 15 14 13 12 11 10 9 8 PJ15 IOR PJ14 IOR PJ13 IOR PJ12 IOR PJ11 IOR PJ10 IOR PJ9 IOR PJ8 IOR Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 PJ7 IOR PJ6 IOR PJ5 IOR PJ4 IOR PJ3 IOR PJ2 IOR PJ1 IOR PJ0 IOR Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W The port J IO register (PJIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port J. Bits PJ15IOR to PJ0IOR correspond to pins PJ15/TI9F to PJ0/TIO2A. PJIOR is enabled when port J pins function as general input/output pins (PJ15 to PJ0) or ATU input/output pins, and disabled otherwise. When port J pins function as PJ15 to PJ0 or ATU input/output pins, a pin becomes an output when the corresponding bit in PJIOR is set to 1, and an input when the bit is cleared to 0. PJIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. |
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