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SH7052 Datasheet(PDF) 681 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 681 Page - Renesas Technology Corp |
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681 / 919 page ![]() 655 • Bit 1—Reserved: This bit always reads 0. The write value should always be 0. • Bit 0—PJ0 Mode Bit (PJ0MD): Selects the function of pin PJ0/TIO2A. Bit 0: PJ0MD Description 0 General input/output (PJ0) (Initial value) 1 ATU input capture input/output compare output (TIO2A) 18.3.20 Port K IO Register (PKIOR) Bit: 15 14 13 12 11 10 9 8 PK15 IOR PK14 IOR PK13 IOR PK12 IOR PK11 IOR PK10 IOR PK9 IOR PK8 IOR Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 PK7 IOR PK6 IOR PK5 IOR PK4 IOR PK3 IOR PK2 IOR PK1 IOR PK0 IOR Initial value: 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W The port K IO register (PKIOR) is a 16-bit readable/writable register that selects the input/output direction of the 16 pins in port K. Bits PK15IOR to PK0IOR correspond to pins PK15/TO8P to PK0/TO8A. PKIOR is enabled when port K pins function as general input/output pins (PK15 to PK0), and disabled otherwise. When port K pins function as PK15 to PK0, a pin becomes an output when the corresponding bit in PKIOR is set to 1, and an input when the bit is cleared to 0. PKIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in hardware standby mode. It is not initialized in software standby mode or sleep mode. |
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