SH7052 datasheet(705/919 Pages) RENESAS

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19.9.1

The port H register configuration is shown in table 19.15.

Table 19.15 Register Configuration

Name

Abbreviation

R/W

Initial Value

Address

Access Size

Port H data register

PHDR

R/W

H'0000

H'FFFFF72C

8, 16

Note:

A register access is performed in four or five cycles regardless of the access size.

19.9.2

Port H Data Register (PHDR)

Bit:

PH15

PH14

PH13

PH12

PH11

PH10

PH9

PH8

Initial value:

R/W:

R/W

Bit:

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

Initial value:

R/W:

R/W

The port H data register (PHDR) is a 16-bit readable/writable register that stores port H data. Bits

PH15DR to PH0DR correspond to pins PH15/D15 to PH0/D0.

When a pin functions as a general output, if a value is written to PHDR, that value is output

directly from the pin, and if PHDR is read, the register value is returned directly regardless of the

pin state. When the

POD pin is driven low, general outputs go to the high-impedance state

regardless of the PHDR value. When the

POD pin is driven high, the written value is output from

the pin.

When a pin functions as a general input, if PHDR is read the pin state, not the register value, is

returned directly. If a value is written to PHDR, although that value is written into PHDR it does

not affect the pin state. Table 19.16 summarizes port H data register read/write operations.

PHDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in

hardware standby mode. It is not initialized in software standby mode or sleep mode.

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