SH7052 datasheet(702/919 Pages) RENESAS

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19.8

Port G

Port G is an input/output port with the 4 pins shown in figure 19.7.

PG3 (I/O) /

IRQ3 (input) /ADTRG0 (input)

PG2 (I/O) /

IRQ2 (input)

PG1 (I/O) /

IRQ1 (input)

PG0 (I/O) /PULS7 (output) /HRxD (input)

Port G

Figure 19.7 Port G

19.8.1

The port G register configuration is shown in table 19.13.

Table 19.13 Register Configuration

Name

Abbreviation

R/W

Initial Value

Address

Access Size

Port G data register

PGDR

R/W

H'0000

H'FFFFF764

8, 16

Note:

A register access is performed in four or five cycles regardless of the access size.

19.8.2

Port G Data Register (PGDR)

Bit:

——

———

—

Initial value:

R/W:

Bit:

——

PG3

PG2

PG1

PG0

Initial value:

R/W:

R/W

The port G data register (PGDR) is a 16-bit readable/writable register that stores port G data. Bits

PG3DR to PG0DR correspond to pins PG3/

IRQ3/ADTRG0 to PG0/PULS7/HRxD0.

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