SH7052 datasheet(699/919 Pages) RENESAS

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19.7

Port F

Port F is an input/output port with the 16 pins shown in figure 19.6.

PF15 (I/O)

PF14 (I/O)

PF13 (I/O)

PF12 (I/O)

PF11 (I/O)

PF10 (I/O)

PF9 (I/O)

PF8 (I/O)

PF7 (I/O)

A21 (output)

A20 (output)

A19 (output)

A18 (output)

A17 (output)

PF6 (I/O)

Port F

BREQ (input)

BACK (output)

CS3 (output)

CS2 (output)

CS1 (output)

CS0 (output)

RD (output)

WAIT (input)

WRH (output)

PF5 (I/O) /A21 (output) /

POD (input)

PF4 (I/O) /A20 (output)

PF3 (I/O) /A19 (output)

PF2 (I/O) /A18 (output)

PF1 (I/O) /A17 (output)

WRL (output)

PF15 (I/O)

ROM disabled

expansion mode

ROM enabled

expansion mode

Single-

chip mode

PF14 (I/O)

PF13 (I/O)

PF12 (I/O)

PF11 (I/O)

PF10 (I/O)

PF9 (I/O)

PF8 (I/O)

PF7 (I/O)

PF5 (I/O) /

POD (input)

PF4 (I/O)

PF3 (I/O)

PF2 (I/O)

PF1 (I/O)

A16 (output)

PF0 (I/O) /A16 (output)

PF0 (I/O)

PF6 (I/O)

Figure 19.6 Port F

19.7.1

The port F register configuration is shown in table 19.11.

Table 19.11 Register Configuration

Name

Abbreviation

R/W

Initial Value

Address

Access Size

Port F data register

PFDR

R/W

H'0000

H'FFFFF74E

8, 16

Note:

A register access is performed in four or five cycles regardless of the access size.

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