SH7052 datasheet(700/919 Pages) RENESAS

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19.7.2

Port F Data Register (PFDR)

Bit:

PF15

PF14

PF13

PF12

PF11

PF10

PF9

PF8

Initial value:

R/W:

R/W

Bit:

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

Initial value:

R/W:

R/W

The port F data register (PFDR) is a 16-bit readable/writable register that stores port F data. Bits

PF15DR to PF0DR correspond to pins PF15/

BREQ to PF0/A16.

When a pin functions as a general output, if a value is written to PFDR, that value is output

directly from the pin, and if PFDR is read, the register value is returned directly regardless of the

pin state. For pins PF0 to PF4, when the

POD pin is driven low, general outputs go to the high-

impedance state regardless of the PFDR value. When the

POD pin is driven high, the written value

is output from the pin.

When a pin functions as a general input, if PFDR is read the pin state, not the register value, is

returned directly. If a value is written to PFDR, although that value is written into PFDR it does

not affect the pin state. Table 19.12 summarizes port F data register read/write operations.

PFDR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in

hardware standby mode. It is not initialized in software standby mode or sleep mode.

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