SH7052 datasheet(696/919 Pages) RENESAS

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19.6

Port E

Port E is an input/output port with the 16 pins shown in figure 19.5.

A15 (output)

A14 (output)

A13 (output)

A12 (output)

A11 (output)

A10 (output)

A9 (output)

A8 (output)

A7 (output)

A5 (output)

A4 (output)

A3 (output)

A2 (output)

A1 (output)

A0 (output)

A6 (output)

Port E

PE15 (I/O) /A15 (output)

PE14 (I/O) /A14 (output)

PE13 (I/O) /A13 (output)

PE12 (I/O) /A12 (output)

PE11 (I/O) /A11 (output)

PE10 (I/O) /A10 (output)

PE9 (I/O) /A9 (output)

PE8 (I/O) /A8 (output)

PE7 (I/O) /A7 (output)

PE5 (I/O) /A5 (output)

PE4 (I/O) /A4 (output)

PE3 (I/O) /A3 (output)

PE2 (I/O) /A2 (output)

PE1 (I/O) /A1 (output)

PE0 (I/O) /A0 (output)

PE6 (I/O) /A6 (output)

PE15 (I/O)

ROM disabled

expansion mode

ROM enabled

expansion mode

Single-

chip mode

PE14 (I/O)

PE13 (I/O)

PE12 (I/O)

PE11 (I/O)

PE10 (I/O)

PE9 (I/O)

PE8 (I/O)

PE7 (I/O)

PE5 (I/O)

PE4 (I/O)

PE3 (I/O)

PE2 (I/O)

PE1 (I/O)

PE0 (I/O)

PE6 (I/O)

Figure 19.5 Port E

19.6.1

The port E register configuration is shown in table 19.9.

Table 19.9

Name

Abbreviation

R/W

Initial Value

Address

Access Size

Port E data register

PEDR

R/W

H'0000

H'FFFFF754

8, 16

Note:

A register access is performed in four or five cycles regardless of the access size.

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