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SH7052 Datasheet(PDF) 694 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 694 Page - Renesas Technology Corp |
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694 / 919 page  668 19.5 Port D Port D is an input/output port with the 14 pins shown in figure 19.4. PD13 (I/O) /PULS6 (output) / HTxD (output) PD12 (I/O) /PULS4 (output) PD11 (I/O) /PULS3 (output) PD10 (I/O) /PULS2 (output) PD9 (I/O) /PULS1 (output) PD8 (I/O) /PULS0 (output) PD7 (I/O) /TIO1H (I/O) PD6 (I/O) /TIO1G (I/O) PD5 (I/O) /TIO1F (I/O) PD3 (I/O) /TIO1D (I/O) PD2 (I/O) /TIO1C (I/O) PD1 (I/O) /TIO1B (I/O) PD0 (I/O) /TIO1A (I/O) PD4 (I/O) /TIO1E (I/O) Port D Figure 19.4 Port D 19.5.1 Register Configuration The port D register configuration is shown in table 19.7. Table 19.7 Register Configuration Name Abbreviation R/W Initial Value Address Access Size Port D data register PDDR R/W H'0000 H'FFFFF746 8, 16 Note: A register access is performed in four or five cycles regardless of the access size. |
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