SH7052 datasheet(196/919 Pages) RENESAS

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Table 9.7

DMAC Internal Status

Item

Address Reload On

Address Reload Off

SAR2

H'FFFFF820

H'FFFFF824

DAR2

H'FFFF6004

DMATCR2

H'0000007C

Bus right

Released

Retained

DMAC operation

Halted

Processing continues

Interrupts

Not issued

Transfer request source flag clear

Executed

Not executed

Notes: 1. Interrupts are executed until the DMATCR2 value becomes 0, and if the IE bit of

CHCR2 is set to 1, are issued regardless of whether address reload is on or off.

2. If transfer request source flag clears are executed until the DMATCR2 value becomes

0, they are executed regardless of whether address reload is on or off.

3. Designate burst mode when using the address reload function. There are cases where

abnormal operation will result if it is used in cycle-steal mode.

4. Designate a multiple of four for the DMATCR2 value when using the address reload

function. There are cases where abnormal operation will result if anything else is

designated.

To execute transfers after the fifth transfer when address reload is on, have the transfer request

source issue another transfer request signal.

9.4.3

Example of DMA Transfer between External Memory and SCI1 Transmitting Side

(Indirect Address On)

In this example, DMAC channel 3 is used, indirect address designated external memory is the

transfer source, and the SCI1 transmitting side is the transfer destination.

Table 9.8 indicates the transfer conditions and the set values of each of the registers.

SH7052 Datasheet(PDF) 196 Page - Renesas Technology Corp