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SH7052 Datasheet(PDF) 292 Page - Renesas Technology Corp

Part # SH7052
Description  SuperHTM RISC engine
PDF  919 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 Datasheet(HTML) 292 Page - Renesas Technology Corp

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266
Timer Interrupt Enable Registers 2A and 2B (TIER2A, TIER2B)
TIER2A: TIER2A controls enabling/disabling of channel 2 input capture, compare-match, and
overflow interrupt requests.
Bit:
15
14
13
12
11
10
9
8
——
——
———
OVE2A
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
IME2H
IME2G
IME2F
IME2E
IME2D
IME2C
IME2B
IME2A
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Bits 15 to 9—Reserved: These bits always read 0. The write value should always be 0.
• Bit 8—Overflow Interrupt Enable 2A (OVE2A): Enables or disables interrupt requests by
OVF2A in TSR2A when OVF2A is set to 1.
Bit 8: OVE2A
Description
0
OVI2A interrupt requested by OVF2A is disabled
(Initial value)
1
OVI2A interrupt requested by OVF2A is enabled
• Bit 7—Input Capture/Compare-Match Interrupt Enable 2H (IME2H): Enables or disables
interrupt requests by IMF2H in TSR2A when IMF2H is set to 1.
Bit 7: IME2H
Description
0
IMI2H interrupt requested by IMF2H is disabled
(Initial value)
1
IMI2H interrupt requested by IMF2H is enabled
• Bit 6—Input Capture/Compare-Match Interrupt Enable 2G (IME2G): Enables or disables
interrupt requests by IMF2G in TSR2A when IMF2G is set to 1.
Bit 6: IME2G
Description
0
IMI2G interrupt requested by IMF2G is disabled
(Initial value)
1
IMI2G interrupt requested by IMF2G is enabled



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