SH7052 datasheet(289/919 Pages) RENESAS

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• Bits 15 to 9—Reserved: These bits always read 0. The write value should always be 0.

• Bit 8—Overflow Interrupt Enable 1A (OVE1A): Enables or disables interrupt requests by

OVF1A in TSR1A when OVF1A is set to 1.

Bit 8: OVE1A

Description

OVI1A interrupt requested by OVF1A is disabled

(Initial value)

OVI1A interrupt requested by OVF1A is enabled

• Bit 7—Input Capture/Compare-Match Interrupt Enable 1H (IME1H): Enables or disables

interrupt requests by IMF1H in TSR1A when IMF1H is set to 1.

Bit 7: IME1H

Description

IMI1H interrupt requested by IMF1H is disabled

(Initial value)

IMI1H interrupt requested by IMF1H is enabled

• Bit 6—Input Capture/Compare-Match Interrupt Enable 1G (IME1G): Enables or disables

interrupt requests by IMF1G in TSR1A when IMF1G is set to 1.

Bit 6: IME1G

Description

IMI1G interrupt requested by IMF1G is disabled

(Initial value)

IMI1G interrupt requested by IMF1G is enabled

• Bit 5—Input Capture/Compare-Match Interrupt Enable 1F (IME1F): Enables or disables

interrupt requests by IMF1F in TSR1A when IMF1F is set to 1.

Bit 5: IME1F

Description

IMI1F interrupt requested by IMF1F is disabled

(Initial value)

IMI1F interrupt requested by IMF1F is enabled

• Bit 4—Input Capture/Compare-Match Interrupt Enable 1E (IME1E): Enables or disables

interrupt requests by IMF1E in TSR1A when IMF1E is set to 1.

Bit 4: IME1E

Description

IMI1E interrupt requested by IMF1E is disabled

(Initial value)

IMI1E interrupt requested by IMF1E is enabled

SH7052 Datasheet(PDF) 289 Page - Renesas Technology Corp