SH7052 datasheet(286/919 Pages) RENESAS

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• Bit 0—Compare-Match Flag 11A (IMF11A): Status flag that indicates GR11A compare-

match.

Bit 0: IMF11A

Description

[Clearing condition]

(Initial value)

When IMF11A is read while set to 1, then 0 is written to IMF11A

[Setting condition]

When TCNT11 = GR11A while GR11A is functioning as an output compare

10.2.6

Timer Interrupt Enable Registers (TIER)

The timer interrupt enable registers (TIER) are 16-bit registers. The ATU-II has 11 TIER registers:

one each for channels 0, 6 to 9, and 11, two each for channels 1 and 2, and one for channels 3 to 5.

For details of channel 10, see section 10.2.26, Channel 10 Registers.

Channel

Abbreviation

Function

TIER0

Controls input capture, and overflow interrupt request

enabling/disabling.

TIER1A, TIER1B

Control input capture, compare-match, and overflow interrupt

TIER2A, TIER2B

request enabling/disabling.

TIER3

Controls input capture, compare-match, and overflow interrupt

request enabling/disabling.

TIER6

Control cycle register compare-match interrupt request

TIER7

enabling/disabling.

TIER8

Controls down-counter output end (low) interrupt request

enabling/disabling.

TIER9

Controls event counter compare-match interrupt request

enabling/disabling.

TIER11

Controls input capture, compare-match, and overflow interrupt

request enabling/disabling.

The TIER registers are 16-bit readable/writable registers that control enabling and disabling of

timer interrupt requests. These cover free-running counter (TCNT) overflow interrupts, channel 0

input capture interrupts, channel 1 to 5 general register input capture/compare-match interrupts,

channel 6 and 7 compare-match interrupts, channel 8 down-counter output pin interrupts, channel

9 event counter compare-match interrupts, and channel 11 general register compare-match

interrupts.

SH7052 Datasheet(PDF) 286 Page - Renesas Technology Corp

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