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SH7052 Datasheet(PDF) 287 Page - Renesas Technology Corp

Part # SH7052
Description  SuperHTM RISC engine
PDF  919 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 Datasheet(HTML) 287 Page - Renesas Technology Corp

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Each TIER is initialized to H'0000 by a power-on reset, and in hardware standby mode and
software standby mode.
Timer Interrupt Enable Register 0 (TIER0)
TIER0 controls enabling/disabling of channel 0 input capture and overflow interrupt requests.
Bit:
15
14
13
12
11
10
9
8
——
——
———
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
——
—
OVE0
ICE0D
ICE0C
ICE0B
ICE0A
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R/W
R/W
R/W
R/W
• Bits 15 to 5—Reserved: These bits always read 0. The write value should always be 0.
• Bit 4—Overflow Interrupt Enable 0 (OVE0): Enables or disables interrupt requests by the
overflow flag (OVF0) in TSR0 when OVF0 is set to 1.
Bit 4: OVE0
Description
0
OVI0 interrupt requested by OVF0 is disabled
(Initial value)
1
OVI0 interrupt requested by OVF0 is enabled
• Bit 3—Input Capture Interrupt Enable 0D (ICE0D): Enables or disables interrupt requests by
the input capture flag (ICF0D) in TSR0 when ICF0D is set to 1. Setting the DMAC while
interrupt requests are enabled allows the DMAC to be activated by an interrupt request.
Bit 3: ICE0D
Description
0
ICI0D interrupt requested by ICF0D is disabled
(Initial value)
1
ICI0D interrupt requested by ICF0D is enabled



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