SH7052 datasheet(300/919 Pages) RENESAS

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Timer Interrupt Enable Registers 6 and 7 (TIER6, TIER7)

TIER6 and TIER7 control enabling/disabling of channel 6 and 7 cycle register compare interrupt

requests.

Bit:

——

———

—

Initial value:

R/W:

Bit:

——

CMExD

CMExC

CMExB

CMExA

Initial value:

R/W:

R/W

x = 6 or 7

• Bits 15 to 4—Reserved: These bits always read 0. The write value should always be 0.

• Bit 3—Cycle Register Compare-Match Interrupt Enable 6D/7D (CME6D/CME7D): Enables or

disables interrupt requests by CMFxD in TSR6 or TSR7 when CMFxD is set to 1. Setting the

DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt

request.

Bit 3: CMExD

Description

CMIxD interrupt requested by CMFxD is disabled

(Initial value)

CMIxD interrupt requested by CMFxD is enabled

x = 6 or 7

• Bit 2—Cycle Register Compare-Match Interrupt Enable 6C/7C (CME6C/CME7C): Enables or

disables interrupt requests by CMFxC in TSR6 or TSR7 when CMFxC is set to 1. Setting the

DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt

request.

Bit 2: CMExC

Description

CMIxC interrupt requested by CMFxC is disabled

(Initial value)

CMIxC interrupt requested by CMFxC is enabled

x = 6 or 7

SH7052 Datasheet(PDF) 300 Page - Renesas Technology Corp