SH7243 datasheet(341/1726 Pages) RENESAS

341 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 311 of 1692

REJ09B0393-0100

There is no access size specification when reading. The correct access start address is output in the

least significant bit of the address, but since there is no access size specification, 16 bits are always

read in case of a 16-bit device. When writing, only the

WEn signal for the byte to be written is

asserted.

It is necessary to output the data that has been read using

RD when a buffer is established in the

data bus. The RD/

WR signal is in a read state (high output) when no access has been carried out.

Therefore, care must be taken when controlling the external data buffer, to avoid collision.

Figures 9.3 and 9.4 show the basic timings of normal space access. If the WM bit in CSnWCR is

cleared to 0, a Tnop cycle is inserted after the CSn space access to evaluate the external wait

(figure 9.3). If the WM bit in CSnWCR is set to 1, external waits are ignored and no Tnop cycle is

inserted (figure 9.4).

A25 to A0

RD/

D15 to D0

WEn

D15 to D0

DACKn

WAIT

CSn

Tnop

Read

Write

Note: * The waveform for DACKn is when active low is specified.

Figure 9.3 Continuous Access for Normal Space 1

Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 0

(Access Wait = 0, Cycle Wait = 0)

SH7243 Datasheet(PDF) 341 Page - Renesas Technology Corp