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SH7243 Datasheet(PDF) 340 Page - Renesas Technology Corp |
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SH7243 Datasheet(HTML) 340 Page - Renesas Technology Corp |
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340 / 1726 page  Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 310 of 1692 REJ09B0393-0100 9.5.2 Normal Space Interface (1) Basic Timing For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see section 9.5.8, SRAM Interface with Byte Selection. Figure 9.2 shows the basic timings of normal space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. CK Note: * The waveform for DACKn is when active low is specified. A25 to A0 RD/ WR RD/ WR D15 to D0 DACKn CSn T1 T2 RD WEn BS D15 to D0 Read Write * Figure 9.2 Normal Space Basic Access Timing (Access Wait 0) |
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