SH7243 datasheet(336/1726 Pages) RENESAS

336 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 306 of 1692

REJ09B0393-0100

Table 9.5

32-Bit External Device Access and Data Alignment in Big-Endian Mode (Only

in SH7286)

Data Bus

Strobe Signals

Operation

D31 to D24

D23 to D16

D15 to D8

D7 to D0

WRHH,

DQMUU

WRHL,

DQMUL

WRH,

DQMLU

WRL,

DQMLL

Byte access at 0

Data 7 to 0



Assert



Byte access at 1



Data 7 to 0



Assert



Byte access at 2



Data 7 to 0



Assert



Byte access at 3



Data 7 to 0



Assert

Word access at 0

Data 15 to 8

Data 7 to 0



Assert



Word access at 2



Data 15 to 8

Data 7 to 0



Assert

Longword access

at 0

Data 31 to 24 Data 23 to 16 Data 15 to 8

Data 7 to 0

Assert

Table 9.6

16-Bit External Device Access and Data Alignment in Big-Endian Mode

Data Bus

Strobe Signals

Operation

D15 to D8

D7 to D0

WRH, DQMLU WRL, DQMLL

Byte access at 0

Data 7 to 0



Assert



Byte access at 1



Data 7 to 0



Assert

Byte access at 2

Data 7 to 0



Assert



Byte access at 3



Data 7 to 0



Assert

Word access at 0

Data 15 to 8

Data 7 to 0

Assert

Word access at 2

Data 15 to 8

Data 7 to 0

Assert

1st time at 0

Data 23 to 16

Data 31 to 24

Assert

Longword

access at 0

2nd time at 2

Data 7 to 0

Data 15 to 8

Assert

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