SH7243 datasheet(333/1726 Pages) RENESAS

333 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 303 of 1692

REJ09B0393-0100

Bit

Bit Name

Initial

Value

R/W

Description

DTSA

R/W

DTC Short Address Mode

Selects the short address mode in which only three

longwords are required for DTC transfer information

read.

0: Four longwords are read as the transfer information.

The transfer information is arranged as shown in the

figure for normal mode in figure 8.2.

1: Three longwords are read as the transfer information.

The transfer information is arranged as shown in the

figure for short address mode in figure 8.2.

Note: The short address mode can be used only for

transfer between an on-chip peripheral module

and the on-chip RAM because the upper eight

bits of SAR and DAR are assumed as all 1s.



Reserved

This bit is always read as 0. The write value should

always be 0.

DTPR

R/W

DTC Activation Priority

Selects whether to start transfer from the first DTC

activation request or according to the DTC activation

priority when multiple DTC activation requests are

generated before the DTC is activated.

Note that DTC transfer is always started according to

the DTC activation priority when multiple DTC activation

requests are generated while the DTC is active.

0: Starts transfer from the DTC activation request

generated first.

1: Starts transfer according to the DTC activation

priority.

Notes: When this bit is set to 1, the following restrictions

apply.

1. The vector information must be stored in the

on-chip ROM or on-chip RAM.

2. The transfer information must be stored in

the on-chip RAM.

3. The function for skipping the transfer

information read step is always disabled.

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