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SH7243 Datasheet(PDF) 330 Page - Renesas Technology Corp

Part # SH7243
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
PDF  1726 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7243 Datasheet(HTML) 330 Page - Renesas Technology Corp

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Section 9 Bus State Controller (BSC)
Rev. 1.00 Jun. 26, 2008 Page 300 of 1692
REJ09B0393-0100
9.4.7
Refresh Time Constant Register (RTCOR)
RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1
and RTCNT is cleared to 0.
When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal.
This request is maintained until the refresh operation is performed. If the request is not processed
when the next matching occurs, the previous request is ignored.
The
REFOUT signal can be asserted when a refresh request is generated while the bus is released.
For details, see the description of Relationship between Refresh Requests and Bus Cycles in
section 9.5.6 (9), Relationship between Refresh Requests and Bus Cycles, and section 9.5.11, Bus
Arbitration.
When the CMIE bit in RTCSR is set to 1, an interrupt request is issued by this matching signal.
The request continues to be output until the CMF bit in RTCSR is cleared. Clearing the CMF bit
only affects the interrupt request and does not clear the refresh request. Therefore, a combination
of refresh request and interval timer interrupt can be specified so that the number of refresh
requests are counted by using timer interrupts while refresh is performed periodically.
When RTCOR is written, the upper 16 bits of the write data must be H'A55A to cancel write
protection. This register is initialized to H'00000000 by a power-on reset and retains the value by a
manual reset and in software standby mode.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9876543210
Bit:
Initial value:
R/W:
0000000000000000
RRRRRRRRRRRRRRRR
0000000000000000
RRRRRRRR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
----------------
--------
Bit
Bit Name
Initial
Value
R/W
Description
31 to 8
All 0
R
Reserved
These bits are always read as 0.
7 to 0
All 0
R/W
8-Bit Register



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