SH7243 datasheet(331/1726 Pages) RENESAS

331 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 301 of 1692

REJ09B0393-0100

9.4.8

Bus Function Extending Register (BSCEHR)

BSCEHR is a 16-bit register that specifies the timing of DTC or DMAC bus release. It is used to

give priority to DTC or DMAC transfer or reduce the number of cycles in which the DTC is

active.

For the differences in DTC operation according to the combinations of the DTLOCK and DTBST

bit settings, refer to section 8.5.9, DTC Bus Release Timing.

Setting the DTSA bit enables DTC short address mode. For details of the short address mode, see

section 8.4, Location of Transfer Information and DTC Vector Table.

The DTPR bit selects the DTC activation priority used when multiple DTC activation requests are

generated before DTC activation.

Do not modify this register while the DMAC or DTC is active.

R/W

Initial value:

R/W:

DTPR

DTSA

DTBST

LOCK

Bit:

76543

Bit

Bit Name

Initial

Value

R/W

Description

DTLOCK

R/W

DTC Lock Enable

Specifies the timing of DTC bus release.

0: The DTC releases the bus when the NOP instruction

is issued after vector read, or after write-back of

transfer information is completed.

1: The DTC releases the bus after vector read, when

the NOP instruction is issued after vector read, after

transfer information read, after a single data transfer,

or after write-back of transfer information.

14 to 12



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

SH7243 Datasheet(PDF) 331 Page - Renesas Technology Corp

SH7243 Datasheet(HTML) 331 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL