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SH7243 Datasheet(PDF) 346 Page - Renesas Technology Corp

Part # SH7243
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
PDF  1726 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7243 Datasheet(HTML) 346 Page - Renesas Technology Corp

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Section 9 Bus State Controller (BSC)
Rev. 1.00 Jun. 26, 2008 Page 316 of 1692
REJ09B0393-0100
When the WM bit in CSnWCR is cleared to 0, the external wait input
WAIT signal is also
sampled.
WAIT pin sampling is shown in figure 9.9. A 2-cycle wait is specified as a software
wait. The
WAIT signal is sampled on the falling edge of CK at the transition from the T1 or Tw
cycle to the T2 cycle.
T1
CK
A25 to A0
CSn
RD/
WR
RD
D15 to D0
WEn
D15 to D0
WAIT
Tw
Tw
Twx
T2
Read
Write
BS
Wait states inserted
by
WAIT signal
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.9 Wait Cycle Timing for Normal Space Access
(Wait Cycle Insertion Using
WAIT Signal)



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