SH7243 datasheet(347/1726 Pages) RENESAS

Part #	SH7243

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

PDF	1726 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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347 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 317 of 1692

REJ09B0393-0100

9.5.4

CSn Assert Period Expansion

The number of cycles from

CSn assertion to RD, WEn assertion can be specified by setting bits

SW1 and SW0 in CSnWCR. The number of cycles from

RD, WEn negation to CSn negation can

be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device

can be obtained. Figure 9.10 shows an example. A Th cycle and a Tf cycle are added before and

after an ordinary cycle, respectively. In these cycles,

RD and WEn are not asserted, while other

signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful

for devices with slow writing operations.

A25 to A0

CSn

RD/

D15 to D0

WEn

D15 to D0

Read

Write

DACKn*

Note: * The waveform for DACKn is when active low is specified.

Figure 9.10

CSn Assert Period Expansion

SH7243 Datasheet(PDF) 347 Page - Renesas Technology Corp