SH7243 datasheet(362/1726 Pages) RENESAS

362 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 332 of 1692

REJ09B0393-0100

(3)

Burst Read

A burst read occurs in the following cases with this LSI.

• Access size in reading is larger than data bus width.

• 16-byte transfer in DMAC

This LSI always accesses the SDRAM with burst length 1. For example, read access of burst

length 1 is performed consecutively 8 times to read 16-byte continuous data from the SDRAM that

is connected to a 16-bit data bus. This access is called the burst read with the burst number 8.

Table 9.14 shows the relationship between the access size and the number of bursts.

Table 9.14

Relationship between Access Size and Number of Bursts

Bus Width

Access Size

Number of Bursts

16 bits

8 bits

16 bits

32 bits

16 bytes

Figures 9.17 and 9.18 show a timing chart in burst read. In burst read, an ACTV command is

output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA

command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external

clock (CK) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an auto-

precharge induced by the READA command in the SDRAM. In the Tap cycle, a new command

will not be issued to the same bank. However, access to another CS space or another bank in the

same SDRAM space is enabled. The number of Tap cycles is specified by the WTRP1 and

WTRP0 bits in CS3WCR.

In this LSI, wait cycles can be inserted by specifying each bit in CS3WCR to connect the SDRAM

in variable frequencies. Figure 9.18 shows an example in which wait cycles are inserted. The

number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where

the READ command is output can be specified using the WTRCD1 and WTRCD0 bits in

CS3WCR. If the WTRCD1 and WTRCD0 bits specify one cycles or more, a Trw cycle where the

NOT command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles

from the Tc1 cycle where the READ command is output to the Td1 cycle where the read data is

latched can be specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0

bits in CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR and WTRCD0 bit in CS3WCR. The

number of cycles from Tc1 to Td1 corresponds to the SDRAM CAS latency. The CAS latency for

the SDRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can

SH7243 Datasheet(PDF) 362 Page - Renesas Technology Corp