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SH7243 Datasheet(PDF) 365 Page - Renesas Technology Corp

Part # SH7243
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
PDF  1726 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7243 Datasheet(HTML) 365 Page - Renesas Technology Corp

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Section 9 Bus State Controller (BSC)
Rev. 1.00 Jun. 26, 2008 Page 335 of 1692
REJ09B0393-0100
(4)
Single Read
A read access ends in one cycle when the data bus width is larger than or equal to the access size.
This, simply stated, is single read. As the SDRAM is set to the burst read with the burst length 1,
only the required data is output. A read access that ends in one cycle is called single read.
Figure 9.19 shows the single read basic timing.
(Tap)
Tr
Tc1
Tde
Td1
CK
A25 to A0
CSn
RD/
WR
RASL
DQMxx
D15 to D0
BS
DACKn*2
A12/A11*1
CASL
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.19 Basic Timing for Single Read (CAS Latency 1, Auto-Precharge)



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