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SH7243 Datasheet(PDF) 368 Page - Renesas Technology Corp

Part # SH7243
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
PDF  1726 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7243 Datasheet(HTML) 368 Page - Renesas Technology Corp

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Section 9 Bus State Controller (BSC)
Rev. 1.00 Jun. 26, 2008 Page 338 of 1692
REJ09B0393-0100
(6)
Single Write
A write access ends in one cycle when the data bus width is larger than or equal to access size. As
a single write or burst write with burst length 1 is set in SDRAM, only the required data is output.
The write access that ends in one cycle is called single write. Figure 9.21 shows the single write
basic timing.
Tap
Tr
Tc1
Trwl
CK
A25 to A0
CSn
RD/
WR
RASL
DQMxx
D15 to D0
BS
DACKn*2
A12/A11*1
CASL
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.21 Single Write Basic Timing (Auto-Precharge)



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