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SH7243 Datasheet(PDF) 372 Page - Renesas Technology Corp |
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SH7243 Datasheet(HTML) 372 Page - Renesas Technology Corp |
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372 / 1726 page ![]() Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 342 of 1692 REJ09B0393-0100 Tc4 Tpw Tp Tc2 Tc3 Tc1 Td4 Td2 Td3 Td1 Tde Tr CK A25 to A0 CS3 RD/ WR RASL DQMxx D15 to D0 BS DACKn*2 A12/A11*1 CASL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.24 Burst Read Timing (Bank Active, Different Row Addresses in the Same Bank, CAS Latency 1) |
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