SH7243 datasheet(370/1726 Pages) RENESAS

370 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 340 of 1692

REJ09B0393-0100

latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of

latency can be acquired even if the DQMxx signal is asserted after the Tc cycle.

When bank active mode is set, if only access cycles to the respective banks in the area 3 space are

considered, as long as access cycles to the same row address continue, the operation starts with the

cycle in figure 9.22 or 9.25, followed by repetition of the cycle in figure 9.23 or 9.26. An access to

a different area during this time has no effect. If there is an access to a different row address in the

bank active state, after this is detected the bus cycle in figure 9.23 or 9.26 is executed instead of

that in figure 9.24 or 9.27. In bank active mode, too, all banks become inactive after a refresh

cycle or after the bus is released as the result of bus arbitration.

Tc4

Tc2

Tc3

Tc1

Td4

Td2

Td3

Td1

Tde

A25 to A0

CS3

RD/

RASL

DQMxx

D15 to D0

DACKn*2

A12/A11*1

CASL

Notes: 1. Address pin to be connected to pin A10 of SDRAM.

2. The waveform for DACKn is when active low is specified.

Figure 9.22 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1)

SH7243 Datasheet(PDF) 370 Page - Renesas Technology Corp