SH7243 datasheet(381/1726 Pages) RENESAS

381 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 351 of 1692

REJ09B0393-0100

(10) Low-Frequency Mode

When the SLOW bit in SDCR is set to 1, output of commands, addresses, and write data, and

fetch of read data are performed at a timing suitable for operating SDRAM at a low frequency.

Figure 9.30 shows the access timing in low-frequency mode. In this mode, commands, addresses,

and write data are output in synchronization with the falling edge of CK, which is half a cycle

delayed than the normal timing. Read data is fetched at the rising edge of CK, which is half a

cycle faster than the normal timing. This timing allows the hold time of commands, addresses,

write data, and read data to be extended.

If SDRAM is operated at a high frequency with the SLOW bit set to 1, the setup time of

commands, addresses, write data, and read data are not guaranteed. Take the operating frequency

and timing design into consideration when making the SLOW bit setting.

Tc1

Td1

Tde

Tap

Tc1

Tnop

Trwl

Tap

(High)

CKE

A25 to A0

CSn

RD/

RASL

DQMxx

D15 to D0

DACKn*2

A12/A11*1

CASL

Notes: 1. Address pin to be connected to pin A10 of SDRAM.

2. The waveform for DACKn is when active low is specified.

Figure 9.30 Low-Frequency Mode Access Timing

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