SH7243 datasheet(424/1726 Pages) RENESAS

424 / 1726 page

Section 10 Direct Memory Access Controller (DMAC)

Rev. 1.00 Jun. 26, 2008 Page 394 of 1692

REJ09B0393-0100

Bit

Bit Name

Initial

Value

R/W

Descriptions

R/(W)* Half-End Flag

This bit is set to 1 when the transfer count reaches half

of the DMATCR value that was specified before

transfer starts.

If DMA transfer ends because of an NMI interrupt, a

DMA address error, or clearing of the DE bit or the

DME bit in DMAOR before the transfer count reaches

half of the initial DMATCR value, the HE bit is not set

to 1. If DMA transfer ends due to an NMI interrupt, a

DMA address error, or clearing of the DE bit or the

DME bit in DMAOR after the HE bit is set to 1, the bit

remains set to 1.

To clear the HE bit, write 0 to it after HE = 1 is read.

0: DMATCR > (DMATCR set before transfer starts)/2

during DMA transfer or after DMA transfer is

terminated

[Clearing condition]

• Writing 0 after reading HE = 1.

1: DMATCR

≤ (DMATCR set before transfer starts)/2

HIE

R/W

Half-End Interrupt Enable

Specifies whether to issue an interrupt request to the

CPU when the transfer count reaches half of the

DMATCR value that was specified before transfer

starts.

When the HIE bit is set to 1, the DMAC requests an

interrupt to the CPU when the HE bit becomes 1.

0: Disables an interrupt to be issued when DMATCR

= (DMATCR set before transfer starts)/2

1: Enables an interrupt to be issued when DMATCR

= (DMATCR set before transfer starts)/2

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