SH7243 datasheet(438/1726 Pages) RENESAS

438 / 1726 page

Section 10 Direct Memory Access Controller (DMAC)

Rev. 1.00 Jun. 26, 2008 Page 408 of 1692

REJ09B0393-0100

Transfer requests from the various modules specify MID and RID as shown in table 10.4.

Table 10.4

DMARS Settings

Peripheral Module

Setting Value for One

Channel ({MID, RID})

MID

RID

Function

H'81

B'01

Receive

USB

H'82

B'100000

B'10

Transmit

RCAN

H'86

B'100001

B'10

Receive

H'89

B'01

Transmit

SSU

H'8A

B'100010

B'10

Receive

H'8D

B'01

Transmit

SCIF_3

H'8E

B'100011

B'10

Receive

H'A1

B'01

Transmit

IIC3

H'A2

B'101000

B'10

Receive

A/D converter_0

H'B3

B'101100

B'11



MTU2_0

H'E3

B'111000

B'11



MTU2_1

H'E7

B'111001

B'11



MTU2_2

H'EB

B'111010

B'11



MTU2_3

H'EF

B'111011

B'11



MTU2_4

H'F3

B'111100

B'11



CMT_0

H'FB

B'111110

B'11



CMT_1

H'FF

B'111111

B'11



When MID or RID other than the values listed in table 10.4 is set, the operation of this LSI is not

guaranteed. The transfer request from DMARS is valid only when the resource select bits

(RS[3:0]) in CHCR0 to CHCR7 have been set to B'1000. Otherwise, even if DMARS has been set,

the transfer request source is not accepted.

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