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SH7243 Datasheet(PDF) 442 Page - Renesas Technology Corp |
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SH7243 Datasheet(HTML) 442 Page - Renesas Technology Corp |
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442 / 1726 page  Section 10 Direct Memory Access Controller (DMAC) Rev. 1.00 Jun. 26, 2008 Page 412 of 1692 REJ09B0393-0100 Table 10.6 Selecting External Request Detection with DL and DS Bits CHCR DL bit DS bit Detection of External Request 0 Low level detection 0 1 Falling edge detection 0 High level detection 1 1 Rising edge detection When DREQ is accepted, the DREQ pin enters the request accept disabled state (non-sensitive period). After issuing acknowledge DACK signal for the accepted DREQ, the DREQ pin again enters the request accept enabled state. When DREQ is used by level detection, there are following two cases by the timing to detect the next DREQ after outputting DACK. Overrun 0: Transfer is terminated after the same number of transfer has been performed as requests. Overrun 1: Transfer is terminated after transfers have been performed for (the number of requests plus 1) times. The DO bit in CHCR selects this overrun 0 or overrun 1. Table 10.7 Selecting External Request Detection with DO Bit CHCR DO bit External Request 0 Overrun 0 1 Overrun 1 |
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