SH7243 datasheet(511/1726 Pages) RENESAS

511 / 1726 page

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 1.00 Jun. 26, 2008 Page 481 of 1692

REJ09B0393-0100

• TSR_5

Bit:

Initial value:

R/W:

7654321

00000000

R/(W)*1 R/(W)*1R/(W)*1

Note:

Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.

CMFU5 CMFV5 CMFW5

Bit

Bit Name

Initial

Value

R/W

Description

7 to 3

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

CMFU5

R/(W)*

Compare Match/Input Capture Flag U5

Status flag that indicates the occurrence of TGRU_5

input capture or compare match.

[Clearing condition]

• When DTC is activated by TGIU_5 interrupt, and the

DISEL bit of MRB in DTC is cleared to 0.

• When 0 is written to CMFU5 after reading CMFU5 = 1

[Setting conditions]

• When TCNTU_5 = TGRU_5 and TGRU_5 is

functioning as output compare register

• When TCNTU_5 value is transferred to TGRU_5 by

input capture signal and TGRU_5 is functioning as

input capture register

• When TCNTU_5 value is transferred to TGRU_5 and

TGRU_5 is functioning as a register for measuring the

pulse width of the external input signal. The transfer

timing is specified by the IOC bits in timer I/O control

registers U_5, V_5, and W_5 (TIORU_5, TIORV_5,

and TIORW_5).*

SH7243 Datasheet(PDF) 511 Page - Renesas Technology Corp

SH7243 Datasheet(HTML) 511 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL