SH7243 datasheet(175/1726 Pages) RENESAS

175 / 1726 page

Section 6 Interrupt Controller (INTC)

Rev. 1.00 Jun. 26, 2008 Page 145 of 1692

REJ09B0393-0100

6.6

Operation

6.6.1

Interrupt Operation Sequence

The sequence of interrupt operations is described below. Figure 6.2 shows the operation flow.

1. The interrupt request sources send interrupt request signals to the interrupt controller.

2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent,

following the priority levels set in interrupt priority registers 01, 02, and 05 to 18 (IPR01,

IPR02, and IPR05 to IPR18). Lower priority interrupts are ignored*. If two of these interrupts

have the same priority level or if multiple interrupts occur within a single IPR, the interrupt

with the highest priority is selected, according to the default priority and IPR setting unit

internal priority shown in table 6.4.

3. The priority level of the interrupt selected by the interrupt controller is compared with the

interrupt level mask bits (I3 to I0) in the status register (SR) of the CPU. If the interrupt

request priority level is equal to or less than the level set in bits I3 to I0, the interrupt request is

ignored. If the interrupt request priority level is higher than the level in bits I3 to I0, the

interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU.

4. When the interrupt controller accepts an interrupt, a low level is output from the

IRQOUT pin.

5. The CPU detects the interrupt request sent from the interrupt controller when the CPU decodes

the instruction to be executed. Instead of executing the decoded instruction, the CPU starts

interrupt exception handling (figure 6.4).

6. The interrupt exception service routine start address is fetched from the exception handling

vector table corresponding to the accepted interrupt.

7. The status register (SR) is saved onto the stack, and the priority level of the accepted interrupt

is copied to bits I3 to I0 in SR.

8. The program counter (PC) is saved onto the stack.

9. The CPU jumps to the fetched interrupt exception service routine start address and starts

executing the program. The jump that occurs is not a delayed branch.

10. A high level is output from the

IRQOUT pin. However, if the interrupt controller accepts an

interrupt with a higher priority than the interrupt just being accepted, the

IRQOUT pin holds

low level.

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