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SH7243 Datasheet(PDF) 187 Page - Renesas Technology Corp

Part # SH7243
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
PDF  1726 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7243 Datasheet(HTML) 187 Page - Renesas Technology Corp

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Section 6 Interrupt Controller (INTC)
Rev. 1.00 Jun. 26, 2008 Page 157 of 1692
REJ09B0393-0100
Figure 6.12 shows the timing for saving to a register bank. Saving to a register bank takes place
between the start of interrupt exception handling and the start of fetching the first instruction in the
interrupt exception service routine.
F
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc
m1
m2
m3
3 Icyc + m1 + m2
IRQ
(1) VTO, PR, GBR, MACL
(2) R12, R13, R14, MACH
(3) R8, R9, R10, R11
(4) R4, R5, R6, R7
(5) R0, R1, R2, R3
Overrun fetch
Saved to bank
D
E
E
MMM
E
F
FD
E
[Legend]
m1:
m2:
m3:
Vector address read
Saving of SR (stack)
Saving of PC (stack)
First instruction in interrupt exception
service routine
Instruction (instruction replacing
interrupt exception handling)
Figure 6.12 Bank Save Timing
(2)
Restoration from Bank
The RESBANK (restore from register bank) instruction is used to restore data saved in a register
bank. After restoring data from the register banks with the RESBANK instruction at the end of the
interrupt service routine, execute the RTE instruction to return from the exception handling.



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