SH7243 datasheet(245/1726 Pages) RENESAS

245 / 1726 page

Section 8 Data Transfer Controller (DTC)

Rev. 1.00 Jun. 26, 2008 Page 215 of 1692

REJ09B0393-0100

Origin of

Activation

Source

Activation

Source

Vector

Number

DTC Vector

Address

Offset

DTCE*

Transfer

Source

Transfer

Destination

Priority

SSRXI

234

H'000007A8 DTCERD5

SSRDR0 to

SSRDR3

Any location*

High

SSU

SSTXI

235

H'000007AC DTCERD4

Any location*

SSTDR0 to

SSTDR3

RXI4

237

H'000007B4 DTCERD3

SCRDR_4

Any location*

SCI4

TXI4

238

H'000007B8 DTCERD2

Any location*

SCTDR_4

RXI0

241

H'000007C4 DTCERE15 SCRDR_0

Any location*

SCI0

TXI0

242

H'000007C8 DTCERE14 Any location*

SCTDR_0

RXI1

245

H'000007D4 DTCERE13 SCRDR_1

Any location*

SCI1

TXI1

246

H'000007D8 DTCERE12 Any location*

SCTDR_1

RXI2

249

H'000007E4 DTCERE11 SCRDR_2

Any location*

SCI2

TXI2

250

H'000007E8 DTCERE10 Any location*

SCTDR_2

RXI3

254

H'000007F8 DTCERE9

SCFRDR_3

Any location*

SCIF3

TXI3

255

H'000007FC DTCERE8

Any location*

SCFTDR_3

Low

Notes: 1. The DTCE bits with no corresponding interrupt are reserved, and the write value should

always be 0.

2. An external memory, a memory-mapped external device, an on-chip memory, or an on-

chip peripheral module (except for DTC, BSC, UBC, AUD, FLASH, and DMAC) can be

selected as the source or destination. Note that at least either the source or destination

must be an on-chip peripheral module; transfer cannot be done among an external

memory, a memory-mapped external device, and an on-chip memory.

3. Read to a message control field in mailbox 0 by using a block transfer mode or etc.

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