SH7243 datasheet(305/1726 Pages) RENESAS

305 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 275 of 1692

REJ09B0393-0100

Bit

Bit Name

Initial

Value

R/W

Description

MPX-I/O Interface Bus Width Specification

Specifies an address to select the bus width when the

BSZ[1:0] of CS5BCR are specified as 11. This bit is

valid only when area 5 is specified as MPX-I/O. Always

set this bit to 0 in the SH7285 and SH7243.

0: Selects the bus width by address A14

1: Selects the bus width by address A21

The relationship between the SZSEL bit and bus width

selected by A14 or A21 are summarized below.

SZSEL

A14

A21

Bus Width

Not affected

8 bits

Not affected

16 bits

Not affected

8 bits

Not affected

16 bits

SZSEL

R/W

MPXW

R/W

MPX-I/O Interface Address Wait

This bit setting is valid only when area 5 is specified as

MPX-I/O. Specifies the address cycle insertion wait for

MPX-I/O interface.

0: Inserts no wait cycle

1: Inserts 1 wait cycle

BAS

R/W

SRAM with Byte Selection Byte Access Select

This bit setting is valid only when area 5 is specified as

SRAM with byte selection.

Specifies the

WEn and RD/WR signal timing when the

SRAM interface with byte selection is used.

0: Asserts the

WEn signal at the read timing and

asserts the RD/

WR signal during the write access

cycle.

1: Asserts the

WEn signal during the read access cycle

and asserts the RD/

WR signal at the write timing.



Reserved

This bit is always read as 0. The write value should

always be 0.

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