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SH7243 Datasheet(PDF) 304 Page - Renesas Technology Corp

Part # SH7243
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
PDF  1726 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7243 Datasheet(HTML) 304 Page - Renesas Technology Corp

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Section 9 Bus State Controller (BSC)
Rev. 1.00 Jun. 26, 2008 Page 274 of 1692
REJ09B0393-0100
Bit
Bit Name
Initial
Value
R/W
Description
6
WM
0
R/W
External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycle is 0.
0: External wait input is valid
1: External wait input is ignored
5 to 2
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1, 0
HW[1:0]
00
R/W
Delay Cycles from RD,
WEn Negation to Address, CS4
Negation
Specify the number of delay cycles from RD and
WEn
negation to address and
CS4 negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS5WCR
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0000000000000000
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R
R/W
R/W
R/W
0000010100000000
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R/W
----------
SZSEL
MPXW/
BAS
-
WW[2:0]
-
-
-
SW[1:0]
WR[3:0]
WM
-
-
-
-
HW[1:0]
Bit
Bit Name
Initial
Value
R/W
Description
31 to 22
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.



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