SH7243 datasheet(300/1726 Pages) RENESAS

Part #	SH7243

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

PDF	1726 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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300 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 270 of 1692

REJ09B0393-0100

• CS2WCR, CS3WCR

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

0000000000000000

RRRRRRRRRRR

R/W

RRRR

0000010100000000

R/W

-----------

BAS

----

-----

WR[3:0]

------

Bit

Bit Name

Initial

Value

R/W

Description

31 to 21



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

BAS

R/W

SRAM with Byte Selection Byte Access Select

Specifies the

WEn and RD/WR signal timing when the

SRAM interface with byte selection is used.

0: Asserts the

WEn signal at the read timing and

asserts the RD/

WR signal during the write access

cycle.

1: Asserts the

WEn signal during the read access cycle

and asserts the RD/

WR signal at the write timing.

19 to 11



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

SH7243 Datasheet(PDF) 300 Page - Renesas Technology Corp

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