SH7243 datasheet(296/1726 Pages) RENESAS

Part #	SH7243

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

PDF	1726 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 266 of 1692

REJ09B0393-0100

Bit

Bit Name

Initial

Value

R/W

Description

10 to 7

WR[3:0]

1010

R/W

Number of Access Wait Cycles

Specify the number of cycles that are necessary for

read/write access.

0000: No cycle

0001: 1 cycle

0010: 2 cycles

0011: 3 cycles

0100: 4 cycles

0101: 5 cycles

0110: 6 cycles

0111: 8 cycles

1000: 10 cycles

1001: 12 cycles

1010: 14 cycles

1011: 18 cycles

1100: 24 cycles

1101: Reserved (setting prohibited)

1110: Reserved (setting prohibited)

1111: Reserved (setting prohibited)

R/W

External Wait Mask Specification

Specifies whether or not the external wait input is valid.

The specification by this bit is valid even when the

number of access wait cycle is 0.

0: External wait input is valid

1: External wait input is ignored

5 to 2



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

SH7243 Datasheet(PDF) 296 Page - Renesas Technology Corp

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